They, too, wondered that at some point. Even if you have an improbably low fail rate, the defects should break every single chip, right? Turns out, defects in manufacturing chips are not randomly distributed but very much localized. The chances of finding a defect next to another one is larger than finding one anywhere else. Thus, usually only a few chips are affected per wafer.

There are a lot of ways to achieve a higher yield rate, e.g. to increase operating voltages. Although most of the transistors produced could operate at lower voltages, thus being more energy efficient, they tend to apply a higher operating voltage just to be sure that the variances of the manufacturing don't impact the operation.

And there are a lot of other tricks, like identifying corner cases. What are the most affected paths through your ciruits? Or something like this one (don't know if it's still true): Intel never uses the first and last transistor of a row, since they always turn out worse than the others.

Then you start tweaking parameters for a few months and then you hopefully get a fab that can manufacture chips at a yield rate high enough to make a profit.