It's clever because you aren't a memory design or test engineer. This type of problem has been known and tested for since shortly after DRAM was invented.

E.g. here's a 1977 databook from Mostek, at the time the premier DRAM manufacturer: https://archive.org/stream/bitsavers_mostekdataryProducts_17...

Look at these tests in particular:

   Adjacent Row Disturb Refresh
   Column Disturb
   Pattern Sensitivity

Look at the details of the column disturb test:

Column is written with an all ones data pattern an "0" is then written into row of the column 100 times followed by reading all other bits of the column and checking each bit for a logic "1" output. Row of the column is then rewritten to a "1" and the procedure is repeated for rows 1,2,3, ... 63 of the column under test. The entire procedure is then repeated for columns 1-63.

That particular test step is only repeated 100 times, because it's a production test and short test time is critical. You can bet that in design verification the chip was characterized a lot more thoroughly.

The downside of increasing memory sizes over the decades (now literally billions of bits in a single chip rather than thousands) is reduced design margins. So we get rowhammer.

You can bet that rowhammer did not come as any surprise to key engineers at the DRAM manufacturers. They just didn't take it very seriously as a possible real world problem, because the access patterns required to cause it are atypical from those of "normal" operation.