Custom ISA extensions for deep learning, communication, and cryptography
DARPA/MTO
autonomous drones cognitive radio
The radar geeks are gonna love to get their hands on ~250GFLOP, 4watt processor. Custom ISA extensions for deep learning, communication, and cryptography
DARPA/MTO
autonomous drones cognitive radio
The radar geeks are gonna love to get their hands on ~250GFLOP, 4watt processor.https://www-ssl.intel.com/content/dam/www/public/us/en/docum...
What does that mean?
Is possible to design a CPU that ON-DEMAND switch between parallel and linear operation? So, if we have a 1000 cores, it switch to 10 with the linear power of 10 x 10?
In my dreams this was very usefull, but wonder how feasible clould be ;)
Basically the limiting factor in most designs isn't so much arithmetic as fetches and branches. Especially cache misses. Theses are inherently linear operations - if you need to fetch from memory and then jump based on the result, for example.
Superscalar 'cheats' somewhat by spending area to keep the pipeline fed, through branch prediction and suchlike.
The nearest thing is the graphics card, which has a very large number of arithmetic units but less flow control, so you can run the same subroutine on lots of different data in parallel.
Highly multicore chips make a different tradeoff: external memory bandwidth is very limited. Ideal for video codecs etc where you can take a small chunk and chew heavily. Very bad for running random unadapted C code, Java etc.