The qemu support for RISC-V is being upstreamed right now and there is also the Spike RISC-V simulator that you can use. There are various soft CPUs that can be run in FPGAs too.
On a related note, is throwing money at the FPGA vendors going to change the tradeoff, or is QEMU already winning against top-end hardware?
- Multithreaded TCG would let us use multiple host cores (eg allowing parallel builds). MT-TCG is a very new feature even in QEMU.
- Adding virtio 1.0 support would allow us to use much more efficient block devices.
qemu-user exists already and avoids both these issues, however we cannot use it for final builds because of concerns over incorrect building when the kernel isn't a RISC-V kernel. For preliminary test-building it is fine, and very fast on Intel Xeon host hardware.