Carbon nanotube transistors outperform silicon | Hacker News Reader

Carbon nanotube transistors outperform silicon

news.wisc.edu

135 pointsccozan42 comments

I'm glad researchers are making progress on figuring out how to surpass the limitations of silicon. But best to take PR articles like this with a grain of salt of course.

"Carbon nanotube transistors should be able to perform five times faster or use five times less energy than silicon transistors, according to extrapolations from single nanotube measurements."

Well, that's the real trick isn't it? Other factors will come into play when you scale from one transistor to a billion. Heat dissipation, physical size, and practicality of manufacture are all open questions. This technology is still many many years away.

"Carbon Nanotube Valley" doesn't have quite the same ring to it

It would be short-sighted to include nanotubes; what about graphene?

So if anything carbon valley, or maybe, allotrope(s) valley :p

Fullerene Valley

"Carbon Valley" probably.

Let's just call it "Group 14 Valley"

Monster Group (formerly the Baby Monster)

Big data problems in Nanovalley of microservices

This is a pretty vacuous article, definitely recommend tl;dr this one (or a better headline by wisc.edu). They claim to outperform silicon, but there are basically no actual numbers for feature size, leakage current, voltage, switching speed, yield, or anything.

tl;dr: they developed a process that separates out the semiconducting nanotubes from the metalic ones, and coated a 1x1 inch area in 5 minutes. They achieved a current 1.9 times that of silicon. There were no specifics beyond that, including what kind of "current" this was or the technique used to create the transistors.

Paper is here: http://advances.sciencemag.org/content/2/9/e1601240

I don't know a whole lot about transistor characteristics, but their process is debatably scalable (specifically the 5mm/min draw rate for the CNT alignment).

So, outperform silicon on conductivity?

The article isn't any clear about switching frequency. Does anybody know about it?

Also, is that a multi-layer FET like VSLI FETs? The article implies so, but isn't stated anywhere.

Switching frequency of a single transistor is essentially the channel current divided by the gate capacitance. If their gates are of similar size than silicon transistors, 1.9 times greater channel current means 47% less time to switch.

There isn't any doubt that nanotube transistors can ultimately be higher performing than silicon. The problem is getting yon nanotubes to stick to more than 70% of the pads that they're supposed to be sticking to. Even modern silicon processes have the occasional bad transistor but with those it's 1 in 10 million or so, not 1 in ten. For VLSI we really need breakthroughs in getting the nanotubes to go where we want them to.

Not even that, it's how to max produce them. Today transistors are made in batches of trillions with hundreds of billions per silicon wafer and up to billions per chip. Scaling up to that level of mass production, let alone reliability, is a huge leap from where we are today and most likely will require decades of work.

The key advantage of silicon, as I understand it, is that we can mass produce ICs on wafers via light-directed etching and epitaxy. I don't know of an equivalent process for carbon that's been proposed yet.

The way that people currently plan to incorporate carbon into ICs is to create a traditional silicon chip with a number of special pads. When a solution of carbon nanotubes is washed over the chip the tubes stick to the pads and create a connection there. So you would be leveraging all the current silicon technology. The problem is getting an economical source of nanotubes and getting them to stick to the damn pads reliably

Too bad they could also become 21st century's asbestos problem.

http://www.scientificamerican.com/article/carbon-nanotube-da...

Sure if we develop some kind of voracious habit of cracking processors open.

Maybe we will, if we do start putting a chip in everything around us (including our clothes). Then we'd also be more vulnerable to those chips potentially breaking around us, too. It probably still wouldn't be quite as bad as asbestos, though, as that's much more frail.

Well and we were using a LOT of abestos, not a few grams here and there but kilos of the stuff.

Well, some people do have a voracious habit of cracking open chips to take a look inside.

e.g. http://www.visual6502.org/images/6502/index.html http://zeptobars.com/en/read/open-microchip-asic-what-inside... http://www.righto.com/2015/12/creating-high-resolution-integ...

Those people will need to be careful then.

As long as it stays sealed inside a LGA (etc.) package, I can't see it causing any problems.

Oh, you mean like keeping the lead in sealed lead acid batteries? Or the mercury in fluorescent tubes? Or the radioactive elements in the nuclear reactor?

I'm not so confident that we're all that good at containment. If they are indeed dangerous, having them widely distributed makes them readily available for someone to break them open and poison someone. Perhaps they can be designed to self-destruct by rusting/oxidising/etc and become less harmful upon package breach.

> Oh, you mean like keeping the lead in sealed lead acid batteries? Or the mercury in fluorescent tubes? Or the radioactive elements in the nuclear reactor?

Misleading analogy. Chip packages are very different from batteries, fluorescent tubes, and nuclear reactors. The only trait those have in common is "contains hazardous materials", so they cannot be used to predict the behavior of chip packages.

I agree that chip packages are as different from batteries/tubes/reactors as those three things are from each other, but that's pretty much the point. ICs are not immune to catastrophic failure either [1,2]. The analogy, "these things are well contained under normal conditions but not under abnormal conditions", stands.

[1] See first photo here: https://en.wikipedia.org/wiki/Failure_of_electronic_componen...

[2] https://www.youtube.com/watch?v=-cKdh0UygVQ

Seems that would only be an issue during manufacturing and disposal. CPU manufacturing already deals with hazardous materials, so that should not be a huge hurdle. On the disposal side, the hazard could be reduced by stepping up efforts to recycle old parts.

Definitely something to be wary of.

We're not coating pipes or making ceiling tiles with the stuff (yet...)

But when built into diced wafer chips, it's really no more hazardous than most other hazardous materials used in the construction and fabrication of the phone or monitor your reading this comment on right now.

Carbon is not passive unlike asbestos. Leave it on fresh się and it will happily oxidize itself.

Unlikely. This was the original paper : http://www.nature.com/nnano/journal/v3/n7/abs/nnano.2008.111... which is cited by about 1800 later papers.

The challenge is that CNT's are not used in quantity as asbestos is, and they aren't used in ways that allows them to enter the lungs easily. That said, there are interesting therapies that have used CNTs being studied.

I wonder how hyped carbon nanotube technology is. In case of graphene, lots of groups had wonderful results on the theory, on simulations but when it comes to nanofabrication or mass-scale production no much progress is done.

It is like saying that nuclear fusion is wonderful in theory but not so much in practice, while we know that the biggest energy source of our galaxy is coming from a thing that uses fusion to generate its energy. We are at the beginning of the technical era, that first needs to revolutionise energy production and storage that will be required for space travel. I have high hopes in graphene and carbon nanotube tech.

> biggest energy source of our galaxy

You meant the Sun, of course. However, your phrasing sent me on a quest to answer the galactic question. From the following article, I learned that the "supermassive black hole at the centre of the Milky Way" emits "cosmic radiation at petaelectronvolt energies", which fits the bill for largest energy source of our galaxy.

https://www.mpg.de/10390310/acceleration-petaelectronvolt-pr...

On the other hand if your looking at energy by type, fusion wins hands down.

They compare it to silicon. But what about other semiconductors like SiGe, InGaAs, etc.

As far as I know intel&co already aim to integrate some of those into future processes.

IBM/Samsung/GloFo consortium has already demonstrated a 7nm SiGe chip. IBM is also heavily researching carbon-nanotubes transistors, but I doubt we'll see those before 5nm, or even later (so potentially 2025+).

http://arstechnica.com/gadgets/2015/07/ibm-unveils-industrys...

https://www-03.ibm.com/press/us/en/pressrelease/39250.wss

How much will cost to manufacture chips with that technology? Current silicon lithography is a photograph superposition process. Will be "drawing" with carbon nanotubes as cheap, or will require per-transistor "drawing" instead of per-layer lithography?

Performance is complex, in this case the performance is measured in computing capacity for a $ or computing capacity per Watt, and all that at yields not substantially worse than what Silicon can already do.

Just size, clock frequency or any other single parameter does not indicate viability of a technology.

No mention of the performance increase? Are they 10x faster, or .001% faster?

From the article:

> the team’s carbon nanotube transistors achieved current that’s 1.9 times higher than silicon transistors

They say they could be 5x faster or use 5x less energy, based on extrapolations of a single transistor in the article

yes, which still leaves me wondering. the latest silicon transistors also use a lot less energy then they did just a few years ago right. So in what way does it compare to silicon transistors. Compared to 14nm? 10nm? Or in general? For transisters of the same size?

Reply on news.ycombinator.com