Chinese Chipmaker Unveils 64-Core ARM Processor | Hacker News Reader

Chinese Chipmaker Unveils 64-Core ARM Processor

top500.org

113 pointsjcbeard52 comments

That subsequently prompted some speculation that the chip would replace the now-banned Xeon Phi processors in the 100-petaflop upgrade to the Tianhe-2 supercomputer, which was supposed to be revealed in June at ISC 2016. Given that the latter never happened, it’s likely those FT-2000/64 chips were not deployed, or if they were, did not meet expectations.

Hmm..

Process：Manufacturing with 28nm process

And there you go.

Not sure if people are aware, but China doesn't have any sub-28nm (or 22nm?) fabs. TSMC has some of course, but the Taiwanese government is very, very strong on keeping those plants in Taiwan (although they are fine with TSMC etc building less advanced fabs in China).

Until they get a process shrink on this, I think.. well, I'd like to see some independent benchmarks.

Edit: The Samsung Exynos 5433 (4 cores on a 20nm process[1]) maxes out at 3.78 GFLOPS[2] on selected benchmarks. Call it 1 GLOP/core - I find it unlikely that this thing is going to get 500 GFLOPS with 64 cores, even with a higher power consumption.

[1] http://www.anandtech.com/show/8718/the-samsung-galaxy-note-4...

[2] http://www.anandtech.com/show/8718/the-samsung-galaxy-note-4...

> Not sure if people are aware, but China doesn't have any sub-28nm (or 22nm?) fabs.

That isn't true, SMIC has a 28nm process(very low yields, and only fabbing designs from Qualcomm afaik, but supposedly does exist, as far as anyone from the west can reasonably ascertain). [1]

1. http://www.smics.com/eng/press/press_releases_details.php?id...

>> Not sure if people are aware, but China doesn't have any sub-28nm (or 22nm?) fabs.

>That isn't true, SMIC has a 28nm process

I don't understand your comment. 28 is not sub-28.

Whoops, my confusion came from the fact that the article was talking about it being made on a 28nm process, and I thought the criticism was China would be unable to fab it.

Wide vector units could do miracles for their FP performance.

Here is how this Chinese processor claims 512 (single precision) GFLOPS: each core seems to have 128-bit NEON vector instructions, so it can execute 4 32-bit operations per cycle. The core runs at 2 GHz, so that's 8 GFLOPS per core. Times 64 cores = 512 GFLOPS. So yeah their claims check out.

These benchmark numbers you found about the Exynos 5433 are so low probably because "Geekbench 3" is not very good at reaching the maximum theoretical performance, as it runs a bunch of real-world computing tasks. In general you need to hand-code assembly loops of fused-multiply-add instructions to reach the max theoretical perf and clearly this is not what Geekbench does, look at the list of FP workloads it runs: http://support.primatelabs.com/kb/geekbench/geekbench-3-benc...

Not only that but for most workloads you would need lots of memory bandwidth to supply the cores.

It seems this was announced exactly one year ago, not today!

Edit: Though last year's announcement was just the planned specs, perhaps the unveiling here is the prototype itself and not the concept.

[Chinese links] http://www.ltaaa.com/bbs/forum.php?mod=viewthread&tid=364899 http://bbs.kafan.cn/thread-1849400-1-1.html

   "FCBGA package with 2892 pins"

Yikes! Thats pretty dense on the other side, would love to see a picture.

It's a 100 watts, so at 3.3 volts its drawing 30+ amps, so I'm guessing that a good chunk of those pins are power and ground. Is that a good theory?

Modern cores are more like 1V or lower. so more like 100A

That's crazy. Do modern cores not also use local, integrated power regulation? I think I remember an Intel PR release about that, but I don't know the detail.

> Process：Manufacturing with 28nm process

standard Vcc for 28nm is 850-1050mV (varies based on the exact process)

so yeah more like 100A and probably that's all going through the pins without on die power regulation

The inductors are still too big to be on-chip

Intel toyed around with fully integrated inductors even in production but I think they kicked them off chip for thermal reasons.

Intel only recently introduced this feature, and it surely required a lot of R&D. At the time they were most likely the only one, and may still be.

Then they removed it in their most recent chips...

IIRC, the only part they replaced was the controller IC itself. All of the main power components (switching transistors, filter inductors and capacitors) remained off-chip.

Consider that the VRM's have as much or more silicon in them than in the host processor, and they have completely different breakdown voltage and switching speed requirements relative to a CPU.

Here's a picture of it: http://www.phytium.com.cn/Public/Home/images/ban2000.png

Since the page is already on the way down here is a rehost: http://i.imgur.com/beAY5De.png

Look, pixel art.

Thanks to the two of you, it's even more amazing than I though.

Does each CPU have its own path to memory?

Followup question. Now that we know it's 100 amps of current going to the chip. In a conservertive world that would be ~300 power and another ~300 ground pins. (Could be 100 of each)

Lets talk board layers. My best board was two data, one power and one ground. I was nowhere near 100 amps for current needs. How many layers in a motherboard to support this CPU?

I'm thinking that these state of the art chips are really pushing the support infrastructure of board layers and power supplies.

Thanks1

Who still uses 3v3 on these kinds of chips? Even cheap ass FPGAs use 1v8.

At 500 gigaflops, I would buy these in a heartbeat if they were offered for sale to the public. While that's only half the performance of a xeon phi, this is a traditional CPU which makes programming it much more straightforward. Not to mention that the cost would be significantly less.

Nowadays Xeon Phis are traditional CPUs.

This is true! New with the Knights Landing generation: https://en.wikipedia.org/wiki/Xeon_Phi#Knights_Landing

    available in two forms, as a coprocessor or a host processor

512 single precision GFLOPS is not half, but 1/10th the performance of a Xeon Phi (Xeon Phi 7210 is 5325 single precision GFLOPS).

However perhaps this processor beats the Xeon Phi 7210 in perf/price as the latter is horrendously priced at $2438 (list price) as well as perf/watt.

Do you think this 64-core beast would be priced at less than $243?

Probably not, but maybe. This chinese processor is hardly a beast. It is comparable (±20%) in raw GFLOPS to a ~$200 Intel skylake processor: 4-core 3.3GHz i7-6700K is rated 422 single precision GFLOPS.

Die size is 640mm2, die cost is ~$42(asumming TSMC's yields, chinese fabs have much lower yields) - so at volume manufacturing cost(including test and package) is surely less than $100 ,closer to $60-70.

And in large enough volume, assuming 50% gross margins, sure it could be cheaper.

Imagine a Beowulf cluster of these. A personal super-computer. God, I can't believe the only thing that comes to mine about Slashdot is the Beowulf cluster.

Natalie Portman, naked and petrified, covered in hot grits? FP? CowboyNeal? GNAA?

Er, how is a phi not like a traditional CPU? It runs linux, you can use python, c, perl, go, rust, whatever. It's basically an x86 with more cores and a larger vector unit.

I wonder how erlang would work on this, especially in a multi-coprocessor system.

I was just thinking the same thing! I really hope as more cores are available on the same machine we start to see languages like Erlang/Elixir really take off.

A crucial question for fast execution of the BEAM-machine on multiple cores is how expensive message copying between cores is. With that many cores, there's probably no shared memory between all cores. How do the remaining cores communicate? Can the BEAM machine's optimisations take into account communication cost?

I don't know very much about BEAM's internals, but one of the key reasons why Erlang (and therefore Elixir) is able to spin up so many processes is because the processes don't have shared state, or at least they don't have writable shared state; the underlying data structures are all immutable, and this is enforced on a VM level (which is why Elixir's "mutability" is only in terms of which data a given variable holds rather than the data itself).

Given that, my guess would be that Erlang/Elixir/LFE/$INSERT_OTHER_BEAM_BASED_LANGUAGE_HERE would do pretty darn well with a high number of cores. I hope one of these days I'll be able to afford such a machine (whether with this particular ARM processor or something else with a ridiculous number of cores/threads, like a modern POWER or SPARC CPU) or have access to one so that I can experience for myself exactly how darn well :)

It's also worth noting that Erlang has had a lot of design around clusters of independent nodes, which means even more extreme problems when it comes to data copying between nodes. I reckon intercore message copying is significantly more performant than internode message copying.

Do you know what kinds of optimisations Erlang/BEAM does for clusters of independent nodes? Does the user have to tell Erlang/BEAM which thread lives on what node, or does the scheduler handle this automatically?

Internode process spawning happens explicitly, last I checked. It's pretty easy once both nodes are communicating, but not automatic.

In contrast, BEAM's SMP support is automatic AFAICT; the scheduler will happily distribute processes across as many cores as it can access (1 BEAM thread per hardware thread by default, so a quad-core CPU with one thread per core and a dual-core CPU with two threads per core will both be loaded with four BEAM threads unless BEAM is configured to do something else).

Or http://www.ponylang.org for the folks preferring compiled languages.

<pedantry>Erlang (and its descendants) are also compiled languages. They just happen to compile to VM bytecode instead of native machine code (though I do wonder if it's possible to implement BEAM in hardware...)</pedantry>

Ponylang looks pretty cool, though; I'll have to check it out.

Check out the The High-Performance Erlang Project

which compile Erlang to Native code.

Nice slide presentation here: http://insidehpc.com/2016/08/phytium-china-unveils-64-core-a...

I guess that's what happens when you forbid Intel from selling to China

http://wccftech.com/us-government-bans-intel-nvidia-amd-chip...

China has loads of money to throw around... they get what they want.

http://www.extremetech.com/computing/227059-amd-announces-ne...

This appears to a global-cache-coherence chip.

Slides 12-16 http://insidehpc.com/2016/08/phytium-china-unveils-64-core-a...

Each 8-core "panel" has its own L2 and DCU The L3 is globally shared, with the usual cache coherence protocol. 30ns latency for L3 hit.

I am not an expert on cache performance, but this certainly seems like an up-to-date design.

Can anyone compare this to Xeon and Phi ?!

Sounds cool. Does anyone have any benchmarks to get an idea of what this processor can actually do?

A price would also be nice.

512Gflops. But probably it isn't supposed to lead(which requires 14nm), but to use manufacturing fabs fully controlled by china.

The 512Gflops is only an uncorroborated blurb posted in a press release. Thus, its highly doubtful that the chip's real world performance comes anywhere near that value.

It would be very interesting to see real-world benchmarks compiled independently.

I have grown suspicious of powers of 2. 512 anything sounds like a theoretical limit based on the number of cores.

I fear for Intel, AMD, and the US semiconductor industry. This is not competitive with Xeons yet, but it will be.

On the other hand this is good for the future of computing in general. The worst case scenario would be for things to stagnate with no competition, offering no incentive for anyone to push beyond traditional Moore's law type scaling.

Reply on news.ycombinator.com