Intel Prototypes Low-Power Circuits

What the article doesn't mention is how the errors are detected -- in a fool proof fashion and cheaply. I can think of error detection schemes that might be cheap to implement but are not foolproof. For instance for an integer multiplication the parity might be cheap to calculate (and without redoing the whole calculation.)

Thus, the error detection algorithm checks the actual parity with the "correct" parity. That of course falls down for multi bit errors.

Researching the literature a bit:

A different approach (tradeoff precision for power) in GPUs: Energy-precision tradeoffs in mobile Graphics Processing Units (http://iccd.et.tudelft.nl/2008/proceedings/060pool.pdf). Another one (probabilistic chips): http://www.technologyreview.com/energy/20246/.

Edit: Added more detail, formatting.

One-page version here: http://www.technologyreview.com/printer_friendly_article.asp...

This is really innovative and I suspect it will force the rest of the industry to adopt similar technologies.