Haven't followed CPU arch in a very long time so my memory may fail, but the B7700 (1977) based on B5000 (1961) architecture demonstrated what you say on an industrial scale. The machine read in a long 48 bit string of opcodes, mapping them directly to hardware (adders, barrel shifters, inc/dec logic, branch prediction), maximizing throughput by anticipating needs for the next few clocks like setting up and (where possible) execute in different parts of the CPU. Since many operations were already present in pipeline and a cache miss or instruction branch could maybe predicted sooner you could see a long way into the future in some cases. This would leave the memory bus more free for data. And if I remember correctly, it would issue multiple (abstract?) cached stack operations to memory if possible, as the interface was quite sophisticated. And other CPUs could service the stack, SMP, if necessary. I had to troubleshoot these opcodes to the bit level back then, in 1981.