[0] https://www.youtube.com/watch?v=oEuXA0_9feM
[1] https://github.com/ssvb/tinymembench/wiki/Nexus-9-(Tegra-TK1...
I'll have to disagree, I think ARM mostly did the right thing with the A64 instruction set. The AArch32 instruction sets were just getting ridiculous (just having multiple instruction sets for one architecture is pretty messed up), with A32, T32 and a bunch of other extensions (ThumbEE, Jazelle) which pretty much no one used. In addition, the A32 and T32 instruction sets have grown organically over time, with new instructions being crammed in any unused / invalid space, which is how we ended up with one encoding doing this one thing, except if one register is the SP or PC, then that is a whole other instruction or with immediate values being split up over 2, 3, 4 fields. Also, a few features had turned out to be pretty bad ideas: for example access to the PC as a general purpose register is overly complicated to implement in OOO cores (verification cost) and comes with performance penalties, but it still had to be supported; the IT instruction is another fun one, especially in the context of dealing with exceptions.
A64 pretty much takes the set of instructions which has emerged over time, removes the bits which are not suitable any more or were bad ideas in retrospect, fits them cleanly in a new encoding space and removes some of the flexibility which was getting in the way (e.g. VFP having either 16 or 32 double precision registers). I expect AArch32 to be gone from most high performance implementations in a few years, with a software DBT option remaining available for legacy software which still hasn't been ported, which is when the implementers will be able to fully benefit from having a simplified AArch64 compared to AArch32.
Apple has been requiring iOS apps to include 64-bit binaries for more than a year, and in iOS 10 they're publicly shaming 32-bit apps [1] on launch. Wouldn't be surprised at all if 32-bit support is gone from iOS and Apple's SoCs by iOS 12 / 2018.
[1] http://appleinsider.com/articles/16/06/15/ios-10-warns-users...
Edit: These machines also do a lot of cool stuff under the hood. DAISY's native binary format looks more like a CFG than we pure instruction steam. The Crusoe has some really sweet exposed speculation hardware. I'm sure Denver does some really cool stuff too, there's just not a whole lot of publicly available information on it.
What is the acronym "CFG", I wasn't able to find that anywhere.
We fought that battle 15 years ago, and delay slots lost (for general-purpose CPUs).