Custom Processor Speeds Up Robot Motion Planning
spectrum.ieee.org
spectrum.ieee.org
The authors are interested in solving motion planning problems with both fixed and dynamic obstacles. They do this using a combination of offline pre-processing and online search.
During pre-processing a general-purpose PRM (read: state-space graph) is constructed using only information about the movement capabilities of the robot and the location of fixed obstacles in the robot's environment.
At run-time the location of dynamic obstacles is detected and all edges from the PRM which would result in a collision with these dynamic obstacles are pruned away. The remaining problem is easy: just find a shortest path in the remaining graph, from the start location to the goal position.
Anyway, it's this online collision checking operation which they implement in and parallelise with custom hardware.
Neat.
I wonder if in their experiments with software-only planners they also made a distinction between off-line preprocessing and online search? The paper doesn't seem to say. I would hope the comparison is apples-to-apples.
As part of Mr. Lee's good neighbor policy, all Rat Things are programmed never to break the sound barrier in a populated area. But Fido's in too much of a hurry to worry about the good neighbor policy. Jack the sound barrier. Bring the noise.
Wasn't able find any scholarly papers on this particular project searching the various references. Can any supply some more information?
In short: collision detection checking across all of the edges in a PRM graph takes 99% of planning time and can be done compeletely independently.
The article describes results for using a Xeon CPU. The linked paper cites other papers where a GPU was used.
We ended up re doing everything (which overall was a good thing, as we made a lot better decisions from the beginning by redesigning), but that's show biz.
As for primetime, we use Synopsys Synplify Pro for FPGA synthesis, and while it does a better job than Altera/Xilinx's tools, it does no where near as well (and works very differently) compared ot physical aware synthesis from Design Compiler or RC/Genus.
We found that Synplify Pro is not quite as good as the vendor tools (xst/quartus) for FPGA synthesis, but I've not compared them recently.
Actually there used to be a version of DC for FPGAs, but it was not good at all. I think it was not as prepared to duplicate logic or flops as compared with the FPGA specific tools.
Source: I looked at CPU vs GPU vs FPGA vs ASIC for deep learning algorithms.
Would anyone with experience in robotics hazard a guess on how they implement that?