How The Commodore 64 Memory Map Worked [video] | Hacker News Reader

How The Commodore 64 Memory Map Worked [video]

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91 pointslefticus9 comments

The most frustrating, sincerely upsetting experience I ever had was when I was about 13 or 14, and encountered the following code: (roughly)

   10 for x = 53248 to 57343
   20 poke x, peek (x)
   30 next x

When I saw this code - it caused physical angst on my part, as it was obvious that this code did nothing. I knew nothing about memory mapped ROM/RAM banks at the time, but I quickly learned....

I've never had as much fun programming as I did with that Commodore 64 and the Programmers reference manual (and all the Compute! secrets/tips books) - it was the youtube minecraft videos of our time.

That code you posted immediately struck me as wrong--not real C64 code. It took me a minute to realize why: it's in lowercase.

(The C64 defaulted to a character set with only capital letters, to leave more space for graphical characters. There was a mixed-case set available, but no one ever used it except for word processing and text adventures.)

Although if you did switch to the mixed-case set it would show source code in lowercase.

If only you had told me twenty years ago.

Did the video explain why poking one value, N, resulted in a peek of the value 240+N? Did I miss it? Is it just a property of the memory location on the VIC chip?

It did not explain why, I'm assuming it's a property of the VIC, but I haven't looked into it yet.

Here, the are spec'd as unused bits returning 1: http://www.antimon.org/code/vic2.html

Ah, thank you. It appears it is only a 4 bit memory location and the spec says the unused bits always return 1's.

The NMOS logic circuitry of the time had pull-up resistors bringing up the voltages to 5V. Chips would then ground the lines to make 0V. So in many logical views, '1' is the default state, and '0' is the active state. Unconnected bits would often leave the lines at 1.

So, if you ask a chip to read a value, and it asserts 4-bit number on the 8-bit data bus, it would tend to be

  1111xxxx

in binary, or 240+x.

(Note: I don't know if it asserts 4 bits on the bus, and the bus pull-ups keep the upper 4 bits high, or if it's internal to the chip that the bits are naturally pulled up and it in fact asserts all 8 bits. Same net effect, modulo some sub-cycle rise/fall timing.)

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