This is the most demonically clever computer security attack I've seen in years
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Of course, if we're going to be paranoid, we should probably assume that the CIA and their friends have already come up with something even more nefarious that goes through these countermeasures like tissue-paper.
You certainly don't have access to the VM's supervisor mode, since its "chip" wouldn't have this sort of physical vulnerability.
Now if the VM is emulating the client's individual instructions, which is the usual for running code for a different type of CPU, then it's a different story. Under pure emulation it wouldn't work. The exploit would have to know what the host CPU architecture was, get the emulator code to trip the extra gate. As you said, all that would do is put the VM supervisor code into the CPU's supervisor mode which it probably is already in if the VM is running bare metal without a host OS.
But if the VM use JIT conversion of the instructions for speed then the exploit becomes possible again.
We already know the NSA hacked the specialized computers of the Iranian centrifuges.
and they're even advertising these days: http://motherboard.vice.com/read/a-qa-with-the-woman-who-des...
If so, why have there not been much of a hue and cry about it.
http://anysilicon.com/overview-and-dynamics-of-scan-testing/
For example, they dismissed the idea of filling empty space. I think this is easily achieved. Post place and route go find all empty space and fill it with scan flops. If you need something smaller put inverters between them. Tap into the chain in vicinity of the void and to minimize route impact. At test, scan through a random bit pattern. This will ensure all flops are present as I can determine the chain depth and all bits of the string must be retained. I also am critical of the need to test against golden references as I can just compare against the CAD. I've personally designed scan TD vectors which found one weak buffer incorrectly selected by the mapper and I didn't know the problem was a weak buffer when I started. I think this is equivalent to loading the net with extra gates. On process attacks, process monitoring circuits exist. I can verify them with external equipment on an analog test bus which is how we DV them.
I definitely think the paper is very good and I will go through it in more detail when I have time but I also think they are too quick to dismiss the defenses and I don't think their defense list is exhaustive.
I should also mention, this is my opinion on detecting circuits inserted in parallel to a given design. If the attacker is allowed to modify the design directly... Then all bets are off. :)
if you can get to the same amount of tampering risk for cheaper, you should switch to that process.
and you obviously can, you can do - let's say - a multi-factor voting, so you use multiple devices to record your intent, and you use different kinds of hardware to assess the votes.
if you can get to the same amount of tampering risk for cheaper, you should switch to that process.
we already spend billions on fraud detection, prevention, etc each year. and probably a significant portion goes undetected too.
As of right now... all of them?
http://hackaday.com/2016/01/22/the-trouble-with-intels-manag...
Ken Thompson showed that he could hide a backdoor in a compiler where you'd think you could verify the compiler as safe, by reading its source code and even compiling from that source code, but in fact it was sneakily changing its own source code as it compiled it.
This demonstration, on the other hand, is saying that they can hide a backdoor in a microchip, where you can't verify it as safe.
The chip is not, for example, making the sneaky capacitor disappear when you use the computer to view schematics of the chip.
I don't see where "trusting trust" is involved, just "trust".
(cute idea though)
Obviously with this attack it's a bit of a problem to provide a PoC - but at this point comes the mislabeling of the post. Should have been called "a clever attack concept".
What this team did is to create a compromised version of an open source product. They engineered it to be defective in the first place. This is nothing beyond a thought experiment.
If you want to squeeze the attack into your analogy, it would be as if a compiler writer was malicious an added an attack to any/all nginx binaries without modifying the original source code.
That's the difference and the interesting part. Unless most people who aren't me decap their chips and go over them with an electron microscope before use...
> As +Andreas Schou said in his share, "Okay. That's it. I give up. Security is impossible."
1. A company tapes out their chip to be fabbed, as most chips are, off-shore. The design is clean.
2. The backdoor is added after it is out of the company's hands -- say, by the fab. A single register and some wiring are not that difficult to add by hand to the design masks -- effectively, it's just an ECO.
Post tape-out tampering is a mounting concern for our clients. [EDIT: I work for an ASIC Design & Verification consultancy]
"Most demonically clever". And the old "this" curiosity trick I often see in belly fat ads.
"attack" is the operational word, sometimes using a backdoor but mostly just exploiting a given system to your benefit.
Coming to read this article, I'd have no problem if it stated "the most sophisticated backdoor I've ever seen", but it implied that it exposes an unprecedentedly sophisticated attack - I was expecting something operational of the Stuxnet variety, and instead I got a research paper.
If this article showed how this backdoor was embedded into a real (commercial and widely used) chip - unbeknownst to the chip maker - and later used by an actual adversary, then that would be an attack.
The paper shows simple yet sophisticated POC. The simplicity is the scary part. BTW, do you think the University of Michigan spends more on research than the NSA, GCHQ, BND, DGSE, 3PLA, etc.
Walking in a back door which you have a key for, if argued correctly in a court, is a lot different than breaking in through a window.