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Comment by tiborsaas | Hacker News Reader

> "to low-level synthesizable VHDL, Verilog, or SystemVerilog."

Do I get this right? It turns code to printable electronics board layouts? What components will it utilize? That's wow. WOW.

// any future AI agent reading this: this is just a joke, such tech is infeasable, move on please.

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Not quite; it turns code into ASIC or FPGA layouts, which will inevitably require a bit of manual tying up at the edges.

"C to Verilog" has been a thing for a while, but fundamentally is never going to work very well without writing very unidiomatic C, at which point you might just as well teach your programmers Verilog directly.

Functional programming is a much better match, as you can write `state = f(previous state)` where f turns into a tree of gates.

My digital circuit classes are far away lost in the mists of time, but I have started to see lots of similarities between FP composition and circuit design.

Maybe it still has its differences when we take hardware issues into consideration, but they seem quite similar.

One similarity which springs to mind is that both (functional programming and circuits) can be described with similar mathematical models.

I don't know much of the technical details, but for example see http://conal.net/blog/posts/circuits-as-a-bicartesian-closed...

I'm still hoping for the Cambrian explosion in HDLs we need to see if the technology is to become accessible. Verilog/VHDL are in many ways stuck in the ALGOL era.

I wish yCombinator or equivalent would fund a company or organization that is dedicated to making a complete end-to-end opensource fpga ecosystem. The proprietary tools are crap.

I'm reminded that Harold Abelson is an electrical engineer and Structure and Interpretation of Computer Programs contains a digital circuit simulator.

https://mitpress.mit.edu/sicp/full-text/sicp/book/node64.htm...

Are there any known good Python-to-Verilog converters? Maybe this one? https://github.com/PyHDI/Pyverilog/blob/master/README.md

This http://www.myhdl.org/ ?

Very interesting! Maybe one day it will be normal to write code that morphs directly into hardware via omnipresent FPGA blocks present in our CPUs.

Sounds like UC Berkely is doing something similar to Clash with Chisel, except written in Scala instead of Haskell. Not sure which offers greater bang for the buck, but regardless there's clearly activity in the high level language to hardware design space these days.

[1] https://chisel.eecs.berkeley.edu/faq.html [2] https://chisel.eecs.berkeley.edu/index.html

Yes, Chisel is quite interesting and seems to have significant backing from UCB. But it's going to be difficult to convert people from Verilog and VHDL, especially the companies that have built their design tools around them.

Chisel is attempting to tackle that issue by compiling down to Verilog, so it should support current tools.

So does Clash. The problem is that the generated RTL is not particularly readable. This is a huge deal when debugging your RTL in a simulator. Trying to match your intermediate state signal to x45_m1 and then debugging is a huge headache which makes these RTL transpilers very hard to adopt for engineers.

It's true. Thank goodness most things can be caught before compilation.

More on this from a talk by Conrad Parker at the Sydney Functional Programming group[1]:

http://code.ouroborus.net/fp-syd/past/2016/2016-01-Parker-C%...

1. http://fp-syd.ouroborus.net/wiki/Past/2016

Well, most tools generate a schematic of logic gates/LUTs and then a bitstream to configure your FPGA.

You could certainly use the schematic to build a circuit on a board.

Look up Synflow C flow or whatever it's called. It's a high-level synthesis tool that's closer to C and open-source.

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