Cool on it being self-hosting. I watched Chisel with cautious interest pretty closely, so FIRRTL looks pretty interesting to me. You guys mention you've taped out ~10 IC designs - does that mean a total of 10 revisions of say, 2 or 3 base designs? From the docs I've skimmed it the projects goal is purely to target Verilog, right? How extensive is the LVS (you mention "weak equivalence testing" so I presume that's not LVS-as-defined-by-graph-isomorphism and you still need to use Cadence/Mentor/whatever?). Which fab and process did y'all use and ultimately how much time do you think you saved compared to the standard 'take the building blocks that TMSC gives you' route ?

edit: This was in reference to FIRRTL's FAQ[1] which mentions the 10 tape outs, and such. Do you guys have open-source netlists or whatnot?

[1] http://www.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-9....