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Agree that there will be less designs that need the advancing nodes (the number of apps needing 1B transistors per chip is limited), but there will be plenty of opportunities at the system level that warrant the $10M type investment needed.

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Idk. The recent tsmc 16nm finfet process offers great leakage numbers (30pa/um) . coupled with packages that can manage extremly tiny packages like the one from tere-circuit could be really interesting , if it was affordable.

Or the other option is to build multi for chips like marvel with their Lego concept offered, all at advanced nodes, but most of the dies after reused from previous designs.

imho, the only reason to go to 14nm and below is if you are pushing the envelope in terms of performance (HPC) or integration (smartphone). Everything else can probably stay at 28nm or above and be combined with 14-7nm using 2.5D or 3D package integration. Note that unless you are a Tier-1 system player you will "never" be able to get known good dies from a big fabless semi vendor, but taping out twice yourself and combining them yourself is pretty straightforward if you have a good packaging partner (like Amkor/ASE)

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