One problem would be instruction size. On a system with (e.g.) 32 registers, each register can be addressed with 5 bits, while a memory address is 32-64 bits.
"Waterman shows that RVC fetches 25%-30% fewer instruction bits, which reduces instruction cache misses by 20%-25%, or roughly the same performance impact as doubling the instruction cache size."
Larger caches are slower, so just doubling the cache size doesn't necessarily recover the performance lost by larger instructions.
...which makes me wonder why they didn't just make that the standard. x86 is dense and that's partly where its performance comes from.
The base RISC-V was designed to be minimal; for instance, hardware multiply and divide is the M extension. I expect that, once the C (compressed instructions) extension is standardized, most high-performance implementations will include it, since the extra area cost should be minimal compared to the out-of-order machinery; small in-order implementations where area is at a premium and performance is not so important will continue to use only the base 32-bit instructions. There's even a variant, RV32E, which omits half the registers to make the core even smaller.
And not everybody wants to go through the design effort to support variable-length encoding (it's non-trivial and can potentially increase pipeline latency to support it). It very well could become a de facto RISC-V standard, but that remains to be seen.
Instruction fetching and parsing is an important bidimensional bottleneck that does restrict your architecture. It's not a bottleneck for run-time performance because it's predictable and optimized at design time.
Basically, instruction operands are divided into 4 classes:
- G (global): the operand refers to the global memory space and contains an offset and size.
- A (automatic): the operand refers to the current stack frame. The offset is relative to the current base pointer.
- I (immediate)
- T (temporary): this is where intermediate results from computations are stored. For example, the result of `a + b` from `(a + b) * c` would be stored in the T memory space. Upon the end of a statement in the HLL, all values in the temporary space are discarded.
Reference: https://github.com/bbu/quaint-lang/blob/master/src/exec.c
Did you mean stack pointer ? base pointer gets set once where as stack pointer changes between every function call.
> Here is how I implemented a small instruction set for the VM of my experimental language, without using GPRs.
stack pointer is still necessery unless some memory region is predefined as stack pointer.
'A class' can be made more space efficient by dividing stack into 16 chunks and then instruction would only need 4bit to address.
[1] pg 12, para 5.