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Comment by sklogic | Hacker News Reader

You did not get it. MyHDL is simply a macro-processor used to generate an RTL. And generating a sequence of similar, say, module instances is ok even with an imperative language, even Verilog got for loops for this.

Chisel and Clash are not any different.

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You might want to re-read my post again, I'm specifically railing against imperative -> RTL/VHDL/Verilog.

Verilog may have for loops but they're largely used for simulation, they're expensive in terms of synthesized hardware(mostly toolchain/process dependent on how they synthesize) and can only be fixed size.

I've got no issue with Chisel, it's a DSL which I think is a good fit. What I'm arguing against is constructs that don't have a clear mapping to hardware representations which means you have to guess at what the compiler generates(see my Mealy vs Moore comment above).

My understanding is that MyHDL is in fact more like Chisel/Clash, it specifically says "It does not turn arbitrary Python into silicon" in their getting started guide (and as sklogic says).

Yeah, but that feels like round hole/square peg -ish. It's like saying we've got all this stuff over here but don't use it, really, we mean don't!

You're going to spend a ton of docs explaining to the user what parts of the language you can't use rather than having a DSL spec that's clear in what's supported.

With a proper DSL you also don't have to massage language features that don't quite map(say enums for state machines) into a format that it's not meant for.

You have no idea what you're talking about. You're wrong, MyHDL is a proper hardware DSL in Python. You've never used it and you have no idea what you're talking about

MyHDL is exactly the same kind of a eDSL as Chisel. And you have a full control of what it generates, see the examples.

If it's Python, it's not a DSL by definition.

Since you don't seem interested in addressing just one issue(I'm sure I could come up with more) around state machines I don't see any reason in continuing this discussion.

> If it's Python, it's not a DSL by definition.

Scala is not any better. It's exactly the same kind of a eDSL - no macros, nothing, just generating objects in runtime and then serialising this tree into a Verilog code. Nothing fancy.

> around state machines

What state machines?!? It does not have any more features for defining FSMs than an underlying Verilog.

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