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Comment by ghaff | Hacker News Reader

>Weird statement in the article

At this point, process nodes don't map to a particularly well-defined set of feature sizes across vendors. So what I assume they're saying is that what Intel calls 10nm is actually pretty similar in terms of transistor size/density to what TSMC is calling 7nm. (No idea if that's actually true but it's what I believe is being said.)

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Yes. Node sizes and actually physical sizes have no correlation anymore. Smaller nodes are smaller, but nowhere near the sizes suggested by names. The already a decade old 45nm process highlights this nicely: https://en.wikipedia.org/wiki/45_nanometer#Technology_demos Effective sizes are all over the place, and Intel's process in particular is nowhere near 45nm for any relevant dimension. It's similar with more recent technologies (and with 3D transistors, the distance between two arbitrary points becomes even less comparable.)

I've been wondering if EUV will bring things back in line. They say the light sources are not bright enough yet, but isn't doing a 2-4x exposure better than double or triple pattering? If the total time were the same you'd still have the benefit of the shorter wavelength allowing dramatically smaller features. What am I missing?

It isn't 25% as bright as it needs to be - it's more like 1% or 0.1%. The total time isn't the same.

That is not true at all, wafer throughput is a factor 4-5 less... The mistake in the first comment is that with self aligned double patterning you only need one litho step, not two. The same applies for SQDP. And since litho is one of the most expensive steps double patterning is more cost effective.

From a technology point of view the problem with EUV is more the line edge roughness, line width roughness, defects and the reliability... Given, more light will make the job easier

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