How to Kill a Supercomputer: Dirty Power, Cosmic Rays, and Bad Solder
spectrum.ieee.org
spectrum.ieee.org
"Jaguar had 360 terabytes of main memory, all protected by ECC. I and others at the lab set it up to log every time a bit was flipped incorrectly in main memory. When I asked my computing colleagues elsewhere to guess how often Jaguar saw such a bit spontaneously change state, the typical estimate was about a hundred times a day. In fact, Jaguar was logging ECC errors at a rate of 350 per minute."
If I take the 360 TB and scale it down to a laptop with 16 GB of RAM am I seeing errors at a proportional rate?
350 errors / 368 640 GB * 16 GB * 60 minutes * 24 hours = 21.875 memory bits changed per day on a 16 GB laptop
That just seems way too high for average users to have not noticed the lack of ECC, and especially for the Jeff Atwood-type non-ECC server crowd (http://blog.codinghorror.com/to-ecc-or-not-to-ecc/). What am I missing?
But why am I not seeing this when explicitly looking for it? If I run Memtest86 for 24 hours I certainly don't expect to see an average of 22 errors and just treat that as within spec. I expect to see no errors. Is it a problem with the memory tests we're using, do we need ones which just write data once and then wait a day to read and validate it rather than hammering RAM with reads and writes?
If you do not have ECC in your computer, yes you should see some flips.
That should see about 0.7 errors per day if they occur at the rate given in the article.
If it is hard to get the compiler to not optimize away the verification, put the buffer in shared memory, and have the verify be a separate program that verifies once and exits, and then periodically invoke that.
I did something like this for a long time on a home Linux server and never caught an error. However, I did not check the assembly output of the compiler to verify that it was actually reading the buffer, so my test may have been invalid.
I hate to contribute nothing but this complaint, but I'm actually having trouble reading this.
Duplicated ALUs, instruction decoders, and retirement units checking each other are rarer than they should be. It wouldn't add that much cost, since most of the chip real estate today is memory cells for caches. If you fault the CPU on a compare error, rather than trying to recover, it doesn't slow down the CPU at all, or add much complexity. Backup and retry is tougher, but may be unnecessary. The important thing is to detect failure, fail fast, and move the work to another CPU.
[1] http://www.intel.com/content/dam/www/public/us/en/documents/...
I was thinking about this as I read the article. Dedicated cosmic ray detectors are almost certainly more sensitive, have better energy resolution, and cosmic ray localization than watching RAM bits be flipped. But given the relatively large number of supercomputers (compared to large cosmic ray detectors) is there some way to use this information from multiple supercomputers to provide more wide-field coverage of the "cosmic ray sky" and supplement dedicated cosmic-ray detection experiments?
Edit: There's a project/app to use smartphone cameras to make a distributed network of cosmic ray detectors: http://wipac.wisc.edu/deco
Sounds like somebody needs to learn about Erlang.
> In June 2012, members of an international forum composed of vendors, academics, and researchers from the United States, Europe, and Asia met and discussed adding resilience to message-passing interface, or MPI, the programming model used in nearly all supercomputing code. Those present at that meeting voted that the next version of MPI would have no resilience capabilities added to it. So for the foreseeable future, programming models will continue to offer no methods for notification or recovery from faults.
Well, no.
http://web.archive.org/web/20040918131755/http://www.sics.se...
I have read that circuit orientation can have an effect. Mounting the silicon vertically, rather than horizontally, can reduce the surface area exposed to rays.