Tresor – CPU-only AES implementation resistant to RAM cold-boot attacks (2011)
www1.informatik.uni-erlangen.de
www1.informatik.uni-erlangen.de
hence my question.
thanks for answering
where in the intel cpu doc can i see this?
Volume 3A
Chapter 9, Processor Management and Initialization
Table 9-1. IA-32 Processor States Following Power-up, Reset, or INIT
The debug registers are named DR0-3 and will be initialized with 00000000H. I can't find an explicit statement for IA-32e mode (Intel's name for x86_64), but I think it is safe to assume the remaining upper 32 bits will be cleared as well.