Graphics Double Data Rate (GDDR5X) SGRAM Deep Dive

Could the timing of this be something to do with Rambus/RDRAM patents expiring? RDRAM made it to market in the late 90s, so relevant patents could conceivably be from ~1995-1996, and would be expiring around now. I seem to remember QDR being mentioned in the context of RDRAM back in the day (although the stuff that shipped only ever used DDR tech). Or have all the major players already licensed those patents years ago and squeezed out the tech? Or is that 20-year-old tech pretty much obsolete in today's context anyway?

I'm the author of this article.

I put it on the website two weeks ago to kick off Google indexing my site, but most articles are incomplete, including this one.

Still, I think there's a bit more detailed information that why you can find on commercials websites who don't bother to read the JEDEC specs.

The very last line of the article:

> For all its benefits, there's also a downside to having large prefetch sizes: there's the chance of

Is the unfinished sentence a joke about a chance of not reading data completely or did the editor not include something?

It's an interesting article. I don't know much about how RAM is designed, so I enjoyed the discussion of how the clocks work in DDR vs QDR modes. Sadly the article ended abruptly:

  For all its benefits, there's also a downside to having large prefetch sizes: there's the chance of

Inaccuracy in the article

> The vast majority of digital logic works on only the rising edge of the clock. This means that transaction only happen when the clock toggles from 0 to 1, and nothing happens when going from 1 to 0.

Actually the majority of digital circuitry clocks data at the falling edge (0→1) transition. For example when programming SPI bus components it's only the odd outlier that requires the clock polarity to be inversed.