They mentioned this, but didn't compare it to classic electrical chips.
Does anyone know what we have now?
I can't quote exact figures but to give a ballpark figure, we're talking about ~5 picojoules per bit at a distance of less than 10 millimeters. This is on a modern (20 nm) SoC.
So we're talking about a pretty significant improvement in power consumption and communication distances. A modern chip running at 2-4 GHz requires several clock cycles for a bit to reach from one corner of the silicon to another. It's becoming a major hurdle to think about when designing chips.
However, this technology has the potential of bringing performance gains to on-chip memories such as L1 and L2 caches as well as software configurable scratch pad memory. Other possibilities that spring to mind are faster core-to-core communications as well as bundling more cores on a same die as the faster communication makes physically larger dies possible.
disclaimer: I work in the semiconductor industry but this is not my area of expertise, my speculation is as good as anyone else's.