Hacker News Reader

Comment by rkangel | Hacker News Reader

> FPGAs are inherently very regular in structure, so figuring out which bit goes where is pretty trivial.

That is ignoring all the complexity that makes modern FPGAs what they are. Three different variants of LUTs, on board block RAMs, Hard IP blocks, or even a whole ARM subsystem. Even your quoted article says that the reverse engineering was possible because "There are not many different kinds of tiles or special function units".

The interfaces to all of these are complex and change regularly as they release new variants.

You might, with the right team, and after many many months of effort work out most of what you need to program one of the simpler Altera/Xilinx devices. But they're a moving target.

The best analogy I can think of is that every month ARM releases a processor with some changes to the instruction set. Tracking that with an open source compiler if you DID have documentation would be hard enough.

View on HN

The whole ARM subsystem configuration (at least in Zynq-7000) has nothing to do with the FPGA bitstream. It's all about configuring registers and can be done in software (normally by a bootloader) or through JTAG.

The ARM peripherals need to be assigned to I/O pins which happens in the FPGA (PL in Zynq terms). The ARM subsystem has bus connections to programmable logic which happens entirely in the FPGA (e.g., you connect a 16550 UART to the ARM via AXI bus, etc). I'd say Zynq is a far more complex bitstream than just a vanilla FPGA.

>The ARM peripherals need to be assigned to I/O pins which happens in the FPGA (PL in Zynq terms).

ARM "hard" peripherals can be assigned to MIO pins, which have nothing to do with the PL, or EMIO which can be routed through PL to the FPGA pins. In both cases, the user must write to PS registers to configure internal muxes and assign the peripheral to a given set of pins. In the latter you must assign the ARM pin as an input in the PL and route it to a PL output as in any regular FPGA design.

>The ARM subsystem has bus connections to programmable logic which happens entirely in the FPGA (e.g., you connect a 16550 UART to the ARM via AXI bus, etc).

Yes it has but the interconnect subsystem is configured in software not through the bitsream.

> I'd say Zynq is a far more complex bitstream than just a vanilla FPGA.

Zynq's PL is a Xilinx 7 Series fabric, I wouldn't say both are much different in complexity. I'm not saying they're simple, tough...

You're right. I was thinking those were PL features because I set them in Vivado, but they are really just exported in the HDF/XML.

Luckily, there is an ARMARM, which can be parsed and translated into a plausible compiler backend automatically. Pity that FPGA vendors do not have a similarly regular documentation format.

Have you got a source on ARMARM? Google and HN are coming up empty.

You must register with ARM in order to get it (it's free, AFAIR).

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc....

Reply on news.ycombinator.com