Asynchronous circuits: https://en.wikipedia.org/wiki/Asynchronous_circuit
The Caltech Asynchronous Microprocessor (1988) was the first asynchronous microprocessor (1988). Caltech designed and manufactured the world's first fully Quasi Delay Insensitive processor. During demonstrations, the researchers amazed viewers by loading a simple program which ran in a tight loop, pulsing one of the output lines after each instruction. This output line was connected to an oscilloscope. When a cup of hot coffee was placed on the chip, the pulse rate (the effective "clock rate") naturally slowed down to adapt to the worsening performance of the heated transistors. When liquid nitrogen was poured on the chip, the instruction rate shot up with no additional intervention. Additionally, at lower temperatures, the voltage supplied to the chip could be safely increased, which also improved the instruction rate—again, with no additional configuration.
Amazing. I want this right now!
If you haven't read anandtech they have articles covering this, since clock rate scaling increases the difficulty of benchmarking.
An asynchronous ARM64 design with potential more than 3 times better performance per watt will sell like hot cakes.
The extra speed always tempting, but a few real builds and the real world of device variation show why the clocked designs are still used.
Why is device variation a reason against asynchronous design? If anything I'd say that is a reason for it. Clocked designs must account for the worst case variation and reduce the clock speed accordingly. An asynchronous design on the other hand will run as fast as physically possible.
When you do crypto on such systems, part of the information that should be hidden is leaked in the form of EM waves, longer or shorter response times, and current consumption (among others). These leaks of information are called "side channels", and have been successfully used to hack some systems.
Some of the current tricks of proper cryptography include things such as "always do the same amount of computation", "always take the same time", "always consume the same current" in order to try to hide this leak of information. It is tricky with standard "clocked" processors. So it will be even trickier with asynchronous processors.
test
Rickkaksdfhkosghvuiasdjfbvhoenckl;ajvgy8eirbvskl;dvmslvnjsapbvjksnkldfvnslanhvfd no line
line
line
Line
For every weird property you try to use to obfuscate the computation, there is some kind of counter to try to de-obfuscate it. That's why crypto is really hard. If you really want to succeed, the only way is use as many tricks as possible, in order to make the attack really hard, hoping to discourage the attacker into doing something more productive with his life.
See e.g. https://crypto.stanford.edu/~dabo/papers/ssl-timing.pdf for this principle applied to performing timing attacks on a remote server (so network latency serves as a handy-dandy rng).
If you are interested in real-world numbers, there is a comparison of between a GA144(an asynchronous multi-computer chip) and a MSP430(conventional low-power microprocessor) here: http://www.greenarraychips.com/home/documents/greg/WP003-100... The GA144 can execute almost 4000x more instructions per second then MSP430 while consuming over 70x less power for the work done.
Yea, but the MSP430 actually has (a ton of) built in peripherals on it's own die, whereas the FA18 has none; so it's not the greatest comparison of J/MIPS.
The GA144 is so radically different that any comparison to a conventional computer is difficult.