New IoT dev kit runs Linux on dual-core, multithreading MIPS CPU
blog.imgtec.com
blog.imgtec.com
Yet "Kickstarter is not a store".
I also question why a company as big as Imagination needs Kickstarter.
1) Going through resellers and distributors adds a signficant premium. By using Kickstarter, we can sell the kit at a reduced price.
2) Kickstarter enables us to communicate directly to indie developers, makers and other hackers and get their feedback on the product.
3) The funds will help us accelerate development for the open source software stack.
Other companies have used crowdfunding to launch products recently, including Canonical, Sony and - more recently - Pepsi.
There have been some cases where the companies ran out of money before they could deliver on all or any of their promises.
Don't fall for this crap, everyone.
MIPSfpga is a product for universities and academic institutions. There are a number of advantages of MIPSfpga over OpenRISC and RISC-V including:
1. The MIPS architecture is better supported by university text books. It is used as an example of a RISC architecture and an example of a CPU microarchitectural implementation in Patterson & Hennessy and in Harris & Harris
2. MIPSfpga shares Verilog source code with MIPS microAptiv UP - a commercial core that has many licensees including Microchip Technology and Samsung. The university professors have an interest to teach students about a CPU widely used by the industry, not a subset of an architecture, an old implementation of the architecture or a CPU core created only for academic purposes and not deployed by semiconductor companies.
3. The MIPS architecture is backed by a significant software ecosystem that includes a dozen of commercial RTOSes, official Linux support, compilers and debuggers, open source software, etc.
The point of MIPSfpga is not to deliver the solution optimized for a specific line of Xilinx FPGAs (like MicroBlaze) but to teach students general design practices, applicable to both FPGAs and ASICs. The code in MIPSfpga is not FPGA-specific. It uses Xilinx and Altera macros for memory in caches, but generally this is the same code used to make an ASIC.
The main idea of using MIPSfpga is that the students can play with the CPU core, create multicore systems, modify caches, etc. If they invent something useful, they can attract venture investment, buy a commercial license for MIPS microAptiv UP or MIPS M5150 and create their own ASIC design company.
Hope this helps.
I taught an architecture class using Patterson & Hennessy, and I wish I'd known about MIPSfpga at the time (maybe it didn't exist, it was a while ago). That would have definitely been helpful for the more eager students to dig deeper into how all this stuff works.
You can take those two books and apply the basics to Risc-V, develop the same IP, and pay zero - and it's already being used in ASICs as well. In fact it's better if you've never been polluted by seeing the license encumbered works, to prevent any claims about originality.
I thought it was because Imagination bought MIPS, no?
The world is moving towards an ISA-neutral, heterogeneous computing environment. If you look at an SoC today, it is very likely that it uses a combination of CPUs, including ARM, MIPS, ARC etc.