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Comment by mehrdada | Hacker News Reader

Please note that the main purpose of ECC is not to reduce RAM error rate and make it look more reliable, but to help the system stop the process when an unrecoverable memory error occurs as opposed to propagating it and resulting in unpredictable outcomes. The change in the effect of failure is what matters most, not the probability of it. Without ECC, there's often no clear way to realize that the result of a computation is valid or garbage and should be discarded.

(Of course, in extreme scenarios, like at Google scale, even ECC can fail to fail due to multibit errors, but in almost all non-pathological scenarios, SECDED[1] is enough to catch all erroneous cases.)

[1]: http://cr.yp.to/hardware/ecc.html

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Exactly, you want to know when the error is due to memory.

Intel deciding that consumers (including those buying Haswell-E CPUS) do not need ECC really irks me. Textbook market segmentation from a near monopoly.

Currently you can not have your cake and eat it:

You cannot have the best single-thread performance (offered by overclocking Haswell-E series or Skylake 6700k) and have ECC.

So if one is building the ultimate workstation, you have a hard choice, do you go with X99 chipset(no ECC but can overclock) or do you go to the server motherboards with C610 chipsets which are quite limited as far as consumer interests are.

Interesting are the Intel mobile Xeons which now provide a venue for ECC on a laptop.

Asrock's X99 boards can accept Xeons and ECC memory.

Nice catch!

You have to give props for Asrock as they are frequently offering unique motherboard features (like that mini-ITX X99 etc).

However, it still does not change the fact that Xeon v3 models are slower(tops at 3.9Ghz Turbo) single threaded than Haswell-E, so it is the same story just a different chipset, either you get fast single threaded performance with Haswell-E or you get Xeon with ECC.

Take these somewhat similar chips: http://ark.intel.com/products/82931/Intel-Core-i7-5930K-Proc... http://ark.intel.com/products/81900/Intel-Xeon-Processor-E5-...

Why can't we have 5930k with ECC support? Because then some thrifty IT managers would buy those for their low end server needs.

Textbook market segmentation? Xeons have ECC, larger thermal envelope, and some additional testing. Sure they are identical silicon.

Generally if you are willing to give up a single clock bin in exchange for ECC you end up with a cheaper (and cooler) system that's more reliable. Generally if you want the cheapest 4c/8t CPU it's a xeon, NOT an i7.

I don't feel particularly artifically segmented. Additionally the high end desktop motherboards tend to be more expensive than the server boards. Often I find a nice server board at $180 and the nice desktop boards are often another $100. Sure they are marketed to gamers, but I really just want a nice reliable power and cooling and it's not clear which of the cheaper desktop boards are really going to last 24/7 for 5 years.

Today I'd buy the E3-1270 for $339 over the $350 i7-6700k. Keep in mind the k chips are a premium AND they don't come with a fan like the non-k chips do. Sure it's 3.6 - 4 GHz instead of 4.0 to 4.2 GHz, not a particularly noticeable difference, especially since that both thermally throttle as needed.

I think ECC is well justified because it doesn't just detect dimm errorrs, but also motherboard errors, cpu errors, and socket (dimm or cpu) errors. If a node randomly crashes/hangs it's very hard to track down why... unless you have ECC and often will help you pin it down. I'd much rather see something strange show up in mcelog than wait for a hang, or worse a corruption.

Most of my "ecc" errors have actually been motherboard, socket, or (in AMDs case) CPUs. When I look at larger samples some dimms are WAY less reliable than others. Strongly implying it's not high energy particles, but something out of spec.

If it weren't a market segmentation strategy, just like limiting the RAM capacity, then there'd be equivalent 'server' chips for most current 'desktop' feature sets and vice versa. However that is clearly not the case, both in my own shopping experience and in the experience of Jeff Atwood (this is in fact something he complains about in this very article).

ECC would require running and connecting a few more traces, but that would /surely/ be offset by not having to create as many layouts or source/stock as many parts. In the past AMD used to have a competing/selling point of /all/ of their CPUs supporting ECC ram. Today that is not the case, as they too have mirrored (colluded?) Intel's market segmentation strategy.

The newer (haswell or later) Intel gpus DO have ECC for the gpu caches. I guess marketing missed that one or engineering insisted.

Good thoughts. Thanks.

Two questions:

(1) IIRC, some operating systems, seeing some ECC errors, maybe just the uncorrectable ones or maybe also the correctable ones, moved to mark the associated memory, or block of memory, as faulty, maybe stopping the (applications) program using that memory, and continued on. Is this done with current operating systems?

(2) What would Windows Server do with a thread, process, address space or whatever the heck that encountered a memory error detected by ECC, especially one that was uncorrectable?

I'm eager to know since I'm eager to build a server, with ECC memory, and run Windows Server in production.

(1) I have never heard of this behavior, correctable errors will be reported via MCA on Intel and uncorrectable ones will reset the system (and probably be logged in some firmware log).

(2) So as far is I know, the normal consequence of a detected multi bit error will be a system reset.

Yeah, agreed. I found myself wondering why he kept referring to "reliability". Perhaps he defines it to include data integrity, but it didn't come across that way to me. I kept thinking to myself "nobody I know uses ECC just to increase reliability".

I believed that Google from the beginning implemented their own checksum codes in their software to regularly verify the data processed or communicated on their non-ECC computers. And I doubt the open-source software the article author uses does the same?

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