A Mill-like architecture would require a huge register file (alternatively, a huge shift register). Not sure it's a good idea for a TTL design. Accumulator architectures are better suited.
It would seem 4 4-bit word register files are all you could obtain from TI (http://www.ti.com/product/sn74ls670); I haven't dug deeper, but yeah as a bread-board layout you would need a lot of surface area to simulate even the smallest Mill. Cool idea though.