There have been a few projects to generate VHDL/Verilog using an LLVM backend, a quick google brings up some interesting presentations. I imagine constraints similar to those that the links OP brings up are why these aren't more mainstream.
The compilation from the imperative world to digital logic is typically pretty opaque. What ends up happening is that the compiler ends up generating shitty hardware, and either you do or don't have a mental model of the hardware you actually want. If you have the mental model, you end up jiggling the C/CUDA compiler into generating the logic you want in lieu of just being able to tell it up front. If you don't have a mental model, making decent hardware is going to suck, and you're probably better off learning an HDL anyway.
A high level functional approach that still recognizes that you're writing hardware is a nice abstraction.
A high level language suitable for HDL generation must expose much better abstractions for parallelism. CUDA is just the same thing as C, too bound to the underlying architecture.
Something that started with a Verilog/VHDL paradigm but provided higher level abstrations would be nice, a good analogy would be something like how Python is to C.
Edit: System Generator is pretty awesome though!
If anything, a pure functional or declarative model might be a better starting point for high-level synthesis than a C-like imperative language. But most of the R&D seems to be going in the opposite direction.