Altera Discloses Heterogeneous SiP Devices That Integrate HBM2 DRAM with FPGAs | Hacker News Reader

Altera Discloses Heterogeneous SiP Devices That Integrate HBM2 DRAM with FPGAs

newsroom.altera.com

41 pointsluu8 comments

I'm curious what the latency of this memory is.

You can do this without the SIP using something called Hybrid Memory Cube: https://en.wikipedia.org/wiki/Hybrid_Memory_Cube The bandwidth is huge and uses a serdes interface. Even so, it would be nice if there were advancements in low latency high capacity memory (without low latency, you need parallel work to make use of all the bandwidth).

Sounds like Intel's acquisition is working out nicely. Perhaps part of the plan?

I'm skeptical of this post's appropriateness for HN. It's a canned press release, has 17 points and only 1 comment.

Can someone explain the significance (if any)?

It doesn't matter if it's a canned press release or not. What matters if there's something new on the market that's relevant to startups. I'm not an EE so I don't follow it completely, I think their introducing a new line of FPGAs that have on board DRAM. That could be very good news if they're priced right, though I don't see in the article how much ram exactly..

You're asking the same questions I did, ;-).

The reason you're asking the same questions has less to do with lack of domain expertise and more to do with the (lack of) quality info in the press release.

Its not about the onboard RAM (this is not new). Its because of the TYPE of RAM, HBM2 instead of more traditional DDR2/3

Nothing too exciting. Having RAM closer to the die is nice, but it's still DRAM. Incremental progress rather than a quantum leap, as usual. I see some advantage in customers not needing to lay out high-speed memory on their PCB, which can require multiple design cycles to get right.

They're achieving this using Intel's EMIB silicon bridge technology, but that was apparently already available to them as a fab customer.

You might want to read up on HMC; this enables 10X the DRAM bandwidth to the FPGA. Since DRAM bandwidth is a bottleneck for many real applications, this is a big deal.

That said, the PR contains nothing about capacity, latency, nor price, so it's near-pointless.

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