Good point, although the requirement is just that they do not cross a 64B cacheline:
http://www.intel.com/content/dam/www/public/us/en/documents/...
8.1.1 Guaranteed Atomic Operations
The P6 family processors (and newer processors since)
guarantee that the following additional memory operation
will always be carried out atomically:
• Unaligned 16-, 32-, and 64-bit accesses to cached memory that fit within a cache line
The first P6 was Pentium Pro, which came out in 1995. It does go on to say that although modern processors will guarantee atomic operations that cross cache lines, it's a bad practice that can badly hurt performance.