Until about 5 years ago the Power architecture dominated in the CPU performance domain. Saying "IBM is too incompetetent" makes you sound like you don't really know this market.
But where is it used? Is it shrinking? I have no idea, at least everything have shown http://www.theplatform.net/2015/06/04/x86-servers-dominate-t...
Intel is still winning / dominating, there were talks of Google using POWER8, haven't seen anything more. And knowing Intel with a clear Roadmap coming up.
Do Power8 have any place in Cloud Computing?
I too, wish Intel would have more competition, but i dont see the choice of using it. Most of the distributed and In Memory Processing aren't using it. But then I guess i am not the target audience.
Intel's primary microarchitecture is aimed at laptops. It scales reasonably down to large tablet power levels and up to workstation power levels. For the high-performance server market, they can only throw cores and cache at the problem, with some enterprise features bolted on.
IBM's always targeted the high-performance server market. For a while, their Power cores were also being used for workstations and even a desktop by Apple, but that's never been the focus. They include things like decimal arithmetic and SMT and hardware transactional memory and they've been selling the high-end parts at 4-5GHz speeds for a long time.
it's like trying to build a skyscraper on the foundations of a log cabin.. you can get so far up and things will start to sink back into the mud.
The x86 architecture was limited to 32-bit, severely limiting the virtual address space as well as hampering OS implementation with hacks like PAE, so what AMD did is to extend it to 64-bit.
The x86 architecture was not designed for SMP scalability due to the rather strict memory ordering requirements, but most of the architectures with laxer memory models (in particular, Alpha, which was the most lax of all) are out of business today (in fact, of the commercially relevant server architectures today, only POWER has lax memory ordering; SPARC can in theory but is usually configured to run with TSO which is similar to x86).
The x86 architecture was not designed for OS virtualization because various instructions did not trap when executed in user mode, so what Intel and AMD did is define a new protection level ("ring -1") to run the hypervisor so this works efficiently now.
What actual problem do you see with x86 that cannot be solved or worked around by some creative engineering at Intel/AMD?
POWER does the exact same (I can't remember which revision).