Intel's "cripple AMD" function
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The thing to remember is that AMD is a small fraction of the size of Intel, and they have to cover the same market segments. If they try to specialize (say, servers, or notebooks), Intel will just sell that segment at a loss. AMD has to cover everything with only a fraction of the people to stay competitive, and it's really hard.
Even while I was there, we had what I suspect (but have no proof) were incidents of people leaking product plans, roadmaps, etc. (but no IP) to Intel. It's sad, really.
I can't imagine Steve Jobs allowing this to happen at Apple. They have definitely caught people leaking things, and the consequences were swift and unpleasant for the leaker. Why can't AMD catch these people? Is there something preventing them from implementing the same kinds of measures to catch leakers as Apple?
(Using Apple just as an example, of course. I'm sure there are other companies who find leakers and make an example of them through the legal system.)
AMD's culture is just different than Apple's. For one, there are no "secret teams" like iPhone, iTablet, etc. (well, at least none that I knew about). For another, developers have real autonomy to make business decisions, something that would never happen at Apple. For instance, I, a lowly intern, redeployed software to the production line during an emergency. If something went wrong, chips would actually stop rolling out of the factory. I would imagine normal (non-senior) Apple engineers don't have that kind of autonomy.
The other major difference, which perhaps you caught above, is that AMD actually manufactures their own stuff. So, not only are there US engineers, but engineers overseas in the plants that AMD owns, engineers in Dresden, etc. Not to say that foreign engineers are somehow bad, but it is a lot harder to control leaks when you have engineers working literally 24/7 all around the world. And at the scale that you're making your own stuff, there are just more people than there are at Apple, and things are way harder to control. It's like herding cats.
> production line during an emergency. If something went
> wrong, chips would actually stop rolling out of the factory.
While I'm all for letting engineers react to things progressively, that you were in position where a screw up could have shut down a fab as an intern is nothing short of terrifying to me.
To me, the converse is a lot scarier: what if I, feeling no personal responsibility for yield, wasn't there after-hours looking for bugs in the first place? Or what if I did find the critical bug, but had to wait weeks for forms before it was pushed through? Or was blocked by office politics?
There's nothing more disheartening as having a fix for something serious that you can't push through. I've worked at companies like that: taking away the power to break something means taking away the power to make it better.
Not to say that I somehow dislike code reviews or generally fly by the seat of my pants: the situation really was a real emergency. I can't talk specifics, but the bug had already cost more than the damage it would do to if I broke something.
It seems to work for them...
It's less so with leaks between companies. A company that deals this way will never allow the information it gathers to show up like that. Even analysts who will examine the leaked materials will have little (not so little in the case of Intel - they have like two competitors) information about the origins of what they are looking at.
Indeed, you don't wanna mess with Apple: http://news.cnet.com/8301-13579_3-10291701-37.html
Not sure what you mean by this statement. Should AMD get some sort of special consideration because they are smaller than Intel?
That's the point & that is arguably anticompetitive. IE, they are small and they have to spread wide to avoid being open to predatory pricing.
What is AMD's competitive advantage? The best I've ever seen is that they are cheaper than Intel for a given processor class/speed. However that doesn't seem to have gotten them much traction. Competing on price alone rarely makes for a successful company.
You sure?
This is even more significant when the competitive options are significantly limited (eg: processors). In larger markets (eg: automobiles) there is more room for low-cost competitors to make some money, but they are not often powerhouses of the industry.
If you have data to the contrary please post (and by data I mean more than just 1-off examples).
Anyway, since you say "it is fairly established" the burden should be on you to tell me where & by who. What I know is established is that internet marketing gurus speaking to small & micro businesses recommend finding non price differentiators. This arguably makes sense for small businesses where market size is not an issue. Most large companies however, need to go after large markets & that means lower prices.
My old marketing textbooks say that there are two broad positioning strategies & corresponding pricing strategies niche(differentiated) & penetration(low cost). The larger share of the pie usually belongs to the latter with high margins often going to the former.
I would argue that low cost strategies are probably more "stable" since they do not rely on innovation & other constant miracles. Even Apple may flop two or three major products in a row & die again.
Selling at low prices given the same cost structure is not a good survival strategy. "We lose money on every unit but we'll make it up on volume!"
That is a good example of manufacturing companies winning on cost.
Car companies that tried to deliver a low-cost product without the quality behind it (eg Yugo) ultimately failed.
PS: Don't forget the market decides price, you can only really control cost if you want to be more than a nitch player.
Instead, the idea is to do a static dispatch for 'known' chips, which is really bad. When the Core2Duo came out, the version of IPP we used reverted to basic MMX code instead of SSE2, about 2.5x slower. This is just bad code, and it's bad on Intel chips, not just AMD.
Also there is the "optimized for benchmarking" piece. It's not always good to use all your cores for one job, for instance, but a lot of these libraries make the assumption that your CPU has nothing else to do.
Dynamic linking of the OpenMP library is almost certainly not the cause of the slowness you're observing. If you really want to force the Intel OpenMP runtime to use all 8 cores:
export OMP_DYNAMIC=false
export OMP_NUM_THREADS=8
export KMP_LIBRARY=throughput
# "KMP_BLOCKTIME" is how long an idle worker thread
# should enter a blocking wait for more work before
# sleeping, in milliseconds. default value is 200ms
export KMP_BLOCKTIME=1000
# following are needed if you use Intel MKL
export MKL_DYNAMIC=false
export MKL_NUM_THREADS=8
For more info: http://software.intel.com/sites/products/documentation/hpc/c...It's only a question of time. I suspect that if more companies decided to pool resources around GCC (or any other free C compiler, like pcc or clang), they will pretty much bury Intel.
Intel is a chip company. The only conceivable reason for them to want to maintain a C compiler is to make a C compiler that's better than the competition on Intel processors and that sucks as much as possible on competing architectures.
Icc is not a compiler. It's a sales tool.
The reasons ICC are better are many but unrelated to vectorization: one optimization I noticed is that it will compile a set of code that depends heavily on aliasing concerns twice and branch to which code path depending on whether the relevant pointers alias or not. This branch is usually predictable, since the pointers in reality will probably never alias, but it has to abide by the C spec.
There's probably a few dozen more things like this that add up to make it a few percent better than GCC. Though GCC is so buggy and many of its heuristics (especially inlining and storing array/struct elements in registers) so utterly hackneyed that beating it is not extraordinarily difficult..
That way the OS could change it per process/thread/context and the code would be happy.
Weren't the VIAs able to trounce Xeons in some crypto stuff?
Yes, since they had crypto instructions and nobody else did. Now I would expect Westmere to be faster.
It is possible to change the CPUID of AMD processors by using the AMD virtualization instructions. I hope that somebody will volunteer to make a program for this purpose. This will make it easy for anybody to check if their benchmark is fair and to improve the performance of software compiled with the Intel compiler on AMD processors.
As always, with the law it's a bit more complex than it might seem.
Also note that most browser UAs explicitly states "like X."
Of course their are rules against using as a TM something that is not indicative of origin (generic names of products &c.) and so if a name were needed for interoperability purposes then it could well be argued for free use.
I perhaps trolled slightly. Mea culpa.
As for Chrome browser identifying as Safari, I think not, what does Help > About say.
Intel often makes noises about open source, so they should put their money where there mouth is.
Intel does more than just make noises about open source. Their wifi and graphics chip set support has been excellent over the years. Prior to the recent changes at ATI they were pretty much the only company doing that.
My point was if they are truly committed to open source they would do this too, they are after all a hardware company and should compete by making the best hardware.
Caveat emptor.
The bulk of the x86 world uses Microsoft C++ or GCC - end of story.
e.g. http://www.amd.com/us-en/assets/content_type/white_papers_an... v. http://download.intel.com/design/processor/specupdt/320836.p... - these aren't just a couple gotchas you can put on the back of an index card
Regardless of whatever bugs may or may not exist in AMD's chips, it is anti-competitive for Intel's compiler to refuse to enable SSEx extensions on AMD processors that claim compatibility, when the user has requested SSEx instructions to be used, unless Intel has specific knowledge that AMD has never produced a sufficiently bug-free implementation of SSEx.
You're entirely on the mark--the bugs are generally not SSE-related, and are typically worked around at the BIOS level. In addition, these bugs aren't "bugs" in the software sense, but more in the engineering sense; running some specific set of 10 million instructions on 3% of the chips while holding at exactly 28 deg C flips a byte in the L2 cache or something. Not something that's easily reproducible.
OP is also right insofar as there would probably be a few gotchas with weird software that would make some engineer somewhere scratch his head because his for loop returns too quickly every third Monday. That doesn't mean that it's fair for Intel to disable SSEx, but it is probably an accurate observation--AMD and Intel have different bugs.
The results of incorrect code generation on any given platform would more likely be people ceasing to use Intel's compiler, and that's not something they want to deal with, I'm sure. As to it being anti-competitive, there's nothing stopping AMD from making their own compiler that produces more optimal code and trusts everyone's processors to work as advertised. If it produced better results, people would likely use it.
(Of course, if they did that, would people use it?)
Sure there is: time and money. Huge companies that are near-monopolies have enormous reservoirs of both in comparison to the competition.
What Intel is accused of doing is considered anti-competitive because they are not actually improving their product. Instead, they are using their stronger market position to degrade the value of another company's product. This harms the overall market, and particularly the consumers. Hence, it's illegal.
The proper way to do it:
if( CPUIDbits & SSE1_CAPABLE ) {enable SSE1}
if( CPUIDbits & SSE2_CAPABLE ) {enable SSE2}
[etc]
The even better way to do it: if( CPUIDbits & SSE1_CAPABLE ) {enable SSE1}
if( CPUIDbits & SSE2_CAPABLE ) {enable SSE2}
if( CPU is Athlon 64 ) {disable some SSE2 functions}
if( CPU is Pentium-M ) {disable all SSE2 functions}
[etc]
Intel's way of doing it: if( CPU is Pentium 3 ) {enable SSE1}
if( CPU is Pentium 4 ) {enable SSE1/SSE2}
if( CPU is Core 2 ) {enable SSE1/SSE2/SSE3/SSSE3}
[etc]
Practically all sane applications do things the first way; a couple do things the second way. Anyone doing things the third way is just asking for trouble both in terms of future compatibility and resilience to unexpected situations. For example, some VMs disable certain instruction sets, which would result in SIGILLs when using the last method.This is really no better than printer manufacturers putting chips into their cartridges so that they can use the DMCA to prevent third parties from refilling or making compatible cartridges.
I don't really know anything about this compiler, so I'm certainly speculating. My assumption is that one writes some function foo() and the compiler prepends a dispatcher in front which forks (code paths, not processes) to one of N optimized but functionally equivalent codepaths based on the actual processor upon which the code runs.
If the forks are inline, and the cache works in blocks, then you are wasting cache space for code that never runs.
But considering it's intel I'm sure they thought of that.