Comment by taliesinb | Hacker News Reader

Comment by taliesinb | Hacker News Reader

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> n then there's the fact you can deal with exponentially larger numbers with roughly linearly (or polynomial) increasing memory, while if you use analog circuits you have to pay a quadratic cost on the exponential, so ~n^k vs ~exp(2n) power consumption doesn't look good from this pov.

That's true, I feel stupid for not having thought of that!

I'm not an electrical engineer, but with the FETs that modern Intel chips are using, what fraction of their power consumption comes from parasitic gate capacitance, versus other losses?

And if you operated in the linear region, what's the ballpark steady-state I_SD current you'd need on one FET to drive the gate of the next FET?

I think that's what this comes down to: if gate capacitance dominates other losses even in the linear regime, you still win by not having a clock and lots of digital transitions.

You could even imagine exploiting that: apply 'slow' augmentations of the input data that get you the equivalent of a bunch of iterations on a single example batch, while incurring a much smaller fraction of that initial cost because activations aren't going to change nearly as much as switching to a whole new example batch.

"parasitic gate capacitance" - not sure if you want to call it "parasitic", after all, a gate capacitance is what makes everything work!

Power is mainly lost via leakage (the smaller the transistor, the more it leaks), and via interconnect capacitance, which dominates all other capacitances in modern circuits.

> "parasitic gate capacitance" - not sure if you want to call it "parasitic", after all, a gate capacitance is what makes everything work!

Of course, but the 'ideal' FET has zero gate capacitance, despite that being the way they work.

> Power is mainly lost via leakage (the smaller the transistor, the more it leaks), and via interconnect capacitance, which dominates all other capacitances in modern circuits.

Interconnect meaning things like the buses? There's no reason to want a von Neumann architecture for an analog chip. If that leaves leakage, I suppose an analog chip would be the beneficiary of needing a lot fewer transistors per op.

'ideal' FET has zero gate capacitance, despite that being the way they work.

I don't understand this statement. What do you mean? A FET is a capacitor (gate to channel). If a gate has no capacitance, you have no transistor.

Interconnect means wire. This has nothing to do with von Neumann architecture. If you have wires in your circuit, then you have wire capacitance. As transistors get smaller, that capacitance starts to dominate internal transistor capacitances.

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