So SPARC has a cache for the top of the stack, but unlike x86, it isn't transparent and requires operating system support. Or at least, that's my read on it.
IIRC the number of available windows can vary and isn't fixed at 8. The ISA says they exist, but not how many.
I believe the spec says you can have up to 32 windows, implementation dependent. You can have as few as 2, in theory. It's interesting to note that the AMD Am29000 series also used register windows and it could have variable numbers of registers in each window (out of the set of 192 registers).